PLA schematic example
Chapter 4: Programmable Logic Devices 4.1 Chapter Overview This Chapter provides an overview on Programmable Logic Devices (PLDs) form the history of programmable logic devices to the device types. PLDs come in two forms, Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays. For realizing logic circuits, and so are rarely used in practice for that purpose. The first device developed later specifically for implementing logic circuits was the Field-Programmable Logic Array (FPLA), or simply PLA for short. A PLA consists of two levels of logic gates: a program. Nov 18, 2017 Programmable Array Logic: We have seen that PLA device with a Programmable AND array and Programmable OR array. However, Programmable Array Logic programmable logic device with a fixed OR array and a programmable AND array. Because only AND gates are programmable, the PAL is easier to program, but is not as flexible as the PLA. May 15, 2018 Programmable Array Logic (PAL) is a type of Programmable Logic Device (PLD) used to realize a particular logical function. PALs comprise of an AND gate array followed by an OR gate array as shown by Figure 1. However it is to be noted that here only the AND gate array is programmable unlike the OR gate array which has a fixed logic. Programming Array Logic. Programmable Array Logic (PAL) is a commonly used programmable logic device (PLD). It has programmable AND array and fixed OR array. Because only the AND array is programmable, it is easier to use but not flexible as compared to Programmable Logic Array (PLA). PAL’s only limitation is number of AND gates. And fixed connections for the OR array. ¾ The PLA (Programmable Logic Array) has programmable connections for both AND and OR arrays. So it is the most flexible type of PLD. The ROM (Read Only Memory) or PROM (Programmable Read Only Memory): The input lines to the AND array are hard-wired and the output lines to the OR array are programmable.
A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logiccircuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND Gates for N input variables, and for M outputs from PLA, there should be M OR Gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms.
PLAs differ from Programmable Array Logic devices (PALs and GALs) in that both the AND and OR gate planes are programmable.
History[edit]
In 1970, Texas Instruments developed a mask-programmable IC based on the IBM read-only associative memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 JK flip flop for memory. TI coined the term Programmable Logic Array for this device.[1]
Implementation procedure[edit]
- Preparation in SOP (sum of products) form.
- Obtain the minimum SOP form to reduce the number of product terms to a minimum.
- Decide the input connection of the AND matrix for generating the required product term.
- Then decide the input connections of OR matrix to generate the sum terms.
- Decide the connections of invert matrix.
- Program the PLA.
PLA block diagram:
1ST BLOCK | 2ND BLOCK | 3RD BLOCK | 4TH BLOCK | 5TH BLOCK |
---|---|---|---|---|
INPUT BUFFER | AND MATRIX | OR MATRIX | INVERT/ NON INVERT MATRIX | FLIP FLOP OUTPUT BUFFER |
Advantages over read-only memory[edit]
The desired outputs for each combination of inputs could be programmed into a read-only memory, with the inputs being loaded onto the address bus and the outputs being read out as data. However, that would require a separate memory location for every possible combination of inputs, including combinations that are never supposed to occur, and also duplicating data for 'don't care' conditions (for example, logic like 'if input A is 1, then, as far as output X is concerned, we don't care what input B is': in a ROM this would have to be written out twice, once for each possible value of B, and as more 'don't care' inputs are added, the duplication grows exponentially); therefore, a programmable logic array can often implement a piece of logic using fewer transistors than the equivalent in read-only memory. This is particularly valuable when it is part of a processing chip where transistors are scarce (for example, the original 6502 chip contained a PLA to direct various operations of the processor[2]).
Applications[edit]
One application of a PLA is to implement the control over a datapath. It defines various states in an instruction set, and produces the next state (by conditional branching). [e.g. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and will define the actions of the control in state 4]. Programmable logic arrays should correspond to a state diagram for the system.
Other commonly used programmable logic devices are PAL, CPLD and FPGA.
The use of the word 'programmable' does not indicate that all PLAs are field-programmable; in fact many are mask-programmed during manufacture in the same manner as a mask ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPGA (Field-programmable gate array), or less frequently FPLA (Field-programmable logic array).
The Commodore 64 home computer released in 1982 used a '906114-01 PLA' to handle system signals.[3]
See also[edit]
References[edit]
- ^Andres, Kent (October 1970). A Texas Instruments Application Report: MOS programmable logic arrays. Texas Instruments. Bulletin CA-158.
- ^How MOS 6502 Illegal Opcodes really work
- ^arcadecomponents.com - Commodore 906114-01 64 PLA IC
External links[edit]
- 'Programmable Logic Array (PLA)'. cmsc311. University of Maryland. 2003.
- 'PLA (programmable logic array)'. Java Applet. University of Hamburg.
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Programmable Logic Devices (PLDs) are the integrated circuits. They contain an array of AND gates & another array of OR gates. There are three kinds of PLDs based on the type of array(s), which has programmable feature.
- Programmable Read Only Memory
- Programmable Array Logic
- Programmable Logic Array
The process of entering the information into these devices is known as programming. Basically, users can program these devices or ICs electrically in order to implement the Boolean functions based on the requirement. Here, the term programming refers to hardware programming but not software programming.
Programmable Read Only Memory (PROM)
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Read Only Memory (ROM) is a memory device, which stores the binary information permanently. That means, we can’t change that stored information by any means later. If the ROM has programmable feature, then it is called as Programmable ROM (PROM). The user has the flexibility to program the binary information electrically once by using PROM programmer.
PROM is a programmable logic device that has fixed AND array & Programmable OR array. The block diagram of PROM is shown in the following figure.
Here, the inputs of AND gates are not of programmable type. So, we have to generate 2n product terms by using 2n AND gates having n inputs each. We can implement these product terms by using nx2n decoder. So, this decoder generates ‘n’ min terms.
Here, the inputs of OR gates are programmable. That means, we can program any number of required product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PROM will be in the form of sum of min terms.
Example
Let us implement the following Boolean functions using PROM.
$$A(X,Y,Z)=sum mleft ( 5,6,7 right )$$
$$B(X,Y,Z)=sum mleft ( 3,5,6,7 right )$$
The given two functions are in sum of min terms form and each function is having three variables X, Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for producing these two functions. The corresponding PROM is shown in the following figure.
Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of all these min terms. But, only the required min terms are programmed in order to produce the respective Boolean functions by each OR gate. The symbol ‘X’ is used for programmable connections.
Programmable Array Logic (PAL)
PAL is a programmable logic device that has Programmable AND array & fixed OR array. The advantage of PAL is that we can generate only the required product terms of Boolean function instead of generating all the min terms by using programmable AND gates. The block diagram of PAL is shown in the following figure.
Here, the inputs of AND gates are programmable. That means each AND gate has both normal and complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So, we can generate only the required product terms by using these AND gates.
Here, the inputs of OR gates are not of programmable type. So, the number of inputs to each OR gate will be of fixed type. Hence, apply those required product terms to each OR gate as inputs. Therefore, the outputs of PAL will be in the form of sum of products form.
Example
Let us implement the following Boolean functions using PAL.
$$A=XY+X{Z}'$$
$$A=X{Y}'+Y{Z}'$$
The given two functions are in sum of products form. There are two product terms present in each Boolean function. So, we require four programmable AND gates & two fixed OR gates for producing those two functions. The corresponding PAL is shown in the following figure.
The programmable AND gates have the access of both normal and complemented inputs of variables. In the above figure, the inputs X, ${X}'$, Y, ${Y}'$, Z & ${Z}'$, are available at the inputs of each AND gate. So, program only the required literals in order to generate one product term by each AND gate. The symbol ‘X’ is used for programmable connections.
Here, the inputs of OR gates are of fixed type. So, the necessary product terms are connected to inputs of each OR gate. So that the OR gates produce the respective Boolean functions. The symbol ‘.’ is used for fixed connections.
Programmable Logic Array (PLA)
PLA is a programmable logic device that has both Programmable AND array & Programmable OR array. Hence, it is the most flexible PLD. The block diagram of PLA is shown in the following figure.
Here, the inputs of AND gates are programmable. That means each AND gate has both normal and complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So, we can generate only the required product terms by using these AND gates.
Here, the inputs of OR gates are also programmable. So, we can program any number of required product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PAL will be in the form of sum of products form.
Example
Let us implement the following Boolean functions using PLA.
$$A=XY+X{Z}'$$
$$B=X{Y}'+YZ+X{Z}'$$
The given two functions are in sum of products form. The number of product terms present in the given Boolean functions A & B are two and three respectively. One product term, ${Z}'X$ is common in each function.
So, we require four programmable AND gates & two programmable OR gates for producing those two functions. The corresponding PLA is shown in the following figure.
Programmable Array Logic Pdf Free
The programmable AND gates have the access of both normal and complemented inputs of variables. In the above figure, the inputs X, ${X}'$, Y, ${Y}'$, Z & ${Z}'$, are available at the inputs of each AND gate. So, program only the required literals in order to generate one product term by each AND gate.
Programmable Logic Array Tutorial Pdf
All these product terms are available at the inputs of each programmable OR gate. But, only program the required product terms in order to produce the respective Boolean functions by each OR gate. The symbol ‘X’ is used for programmable connections.